1. Field of the Invention
The present invention relates to an image sensor and a fabricating method of the image sensor, and more particularly, to an image sensor and a fabricating method of the image sensor capable of reducing blooming by forming an anti-blooming path between the source follower transistor channel and the photodiode region.
2. Description of the Prior Art
CMOS image sensor (CIS) has been widely adopted in many applications, such as cell phone, webcam, security, toy, medical device, etc. The next big wave of CIS is on the automotive application. It can be used as driver's visual and action assistants for a safe and less stressful driving experience.
However, the requirements to an automobile image sensor are very demanding. They are mostly based on the harsh operation conditions of the automobiles. A key requirement of automotive sensors is low blooming.
Blooming happens when a pixel is filled up with photo carriers (in most cases, electrons) and the integration time is not reached yet. The incoming light still generates more electron/hole pairs but that can not be collected by this pixel anymore. The electrons and holes will be injected into grounded P-well and recombined over there. However, just like the principle of BJT, if there is an “empty” photodiode (PD) nearby as the “collector”, and if electrons can not be fully recombined in such a short distance, they will flow into the empty PD by diffusion. One bright pixel, in this fashion, spreads to several other pixels in the neighboring region. Blooming is highly undesirable in CIS applications, especially automotive and surveillance ones.
The road scene, especially at night, is usually high dynamic range type. The CIS is required to have a good blooming control at ultra-bright region in order to ensure the neighboring dimly lit regions not washed out by the blooming charges. Otherwise, many details must be buried and it is hard for the car control system or the driver to extract the information from the scene. Another reason for low blooming is the request of some High Dynamic Range (HDR) scheme, in which the PDs integration times are different. The blooming of a longer integration PD could destroy the information in the shorter integration one. One more reason is cluster control. Even in the dark and especially at high temperature operation such as in a car, a super “hot” pixel could be filled up by strong dark current and reach blooming level. The adjacent hot pixels display a strange pattern as a hot cluster that is very hard to be corrected by ISP.
There are several prior arts about reducing blooming. In a prior art (Yasuo Ishihara, et al., “Interline CCD Image Sensor with an Antiblooming Structure”, IEEE Transactions on Electron Devices, Vol., ED-31, NO. 1, January 1984), the CCD solution can provide high voltage for solid control of veridical drain “on” an “off” but such a large range of voltage is not available for the CIS.
In another prior art (G. Agranov, et al., “Super Small, Sub 2 μm Pixels For Novel CMOS Image Sensors”, INTERNATIONAL IMAGE SENSOR WORKSHOP, Jun. 7-10, 2007, Ogunquit, Me. USA), the buried N-well design faces trade-off between anti-blooming and red response.
The other conventional solution is using surface anti-blooming drain. In CIS 4T pixel, the transfer gate (Tx) is slightly turned on during integration of the pixel, so blooming charge can be drained to the floating diffusion (FD) region. However, this solution has disadvantages of high leakage current from the Tx channel to the PD region, and increasing dark current and white pixels dramatically, and FWC is also a trade-off in this scheme. To overcome the dark current issue, a dedicated anti-blooming drain can be designed but it will reduce the photo sensing area.
For example, please refer to FIG. 1, FIG. 2, and FIG. 3. FIG. 1 shows a simplified top-view diagram of a conventional image sensor 100. FIG. 2 shows a simplified cross-sectional view (A-A′) diagram of the image sensor 100. FIG. 3 shows an equivalent circuit diagram of the conventional image sensor 100. As shown in FIG. 1, FIG. 2, and FIG. 3, the image sensor 100 comprises: a P type substrate 110, a P type epitaxial layer 120, two photodiode regions 130, 132, two P type well regions 140, 142, a gate region 150 of a source follower (SF) transistor, two STI regions 160, 162, a transfer gate (Tx) 170, a floating diffusion (FD) region 180, a select gate (SEL) 190, a reset gate (RES) 200, a MOS gate oxide 210, and a surface pinning layer 220 of the photodiode regions 130, 132. The MOS gate oxide 210 is included in any CMOS process without exception, and Its stage is almost right before the poly gate formation. The surface pinning layer 220 is not a default CMOS process but necessary for the CIS pixel, and its stage is right after the poly gate formation. Forming surface pinning layer 220 is a standard process step to form the photodiode regions 130, 132. In addition, in another prior, the STI region 160 is replaced by a strong P-well isolation 230, as shown in FIG. 4 and FIG. 5.